Recently, semiconductor memory devices (hereinafter referred to as semiconductor memories) having high-speed access modes such as a page mode or a serial access mode suitable for reading continuous data have been developed so as to meet a demand for faster access to data stored in the semiconductor memories. For example, in an read operation in the serial access mode, a plurality of memory cells in the same row (word line) of a memory cell array are simultaneously selected in accordance with an input address. Then, by changing a predetermined bit in the input address, data in the selected plural memory cells are switched at a high speed so as to be sequentially outputted.
A semiconductor memory disclosed by the Japanese Publication for Laid-Open Patent Application No. 7-98989/1995 (Tokukaihei 7-98989) is arranged as follows: a memory cell array is provided on each side of a row decoder for selecting word lines to be driven, and the memory cell arrays are symmetrically arranged on the sides of the row decoder so as to equalize access time.
The semiconductor memory has memory cell arrays A and B in which memory cells are disposed in a matrix form, as illustrated in FIG. 10. The semiconductor memory further includes row decoders 51 and 52, word line driving circuits 53a and 53b, a column decoder 54, and two bit line selecting circuits 55. The row decoder 51 selects rows corresponding to a row address (A13 through A19), while the row decoder 52 selects rows corresponding to a row address (A8 through A12). The word line driving circuits 53a and 53b drive word lines in accordance with outputs of the row decoders 51 and 52. The column decoder 54 and the bit line selecting circuits 55 select memory cells in a plurality of columns which correspond to a column address (A4 through A7). The semiconductor memory has a capacity of 8M bits (2.sup.23 bits), and an output is set to 8 bits.
Note that 8 bits (D0 through D7) constitute one word, and 16 words (W0 through W15) constitute one page. And, in one word line, data of 16 pages (P0 through P15), that is, data of 2.sup.3 .times.2.sup.4 .times.2.sup.4 =2.sup.11 bits, are stored. The data are divided into two so as to be respectively stored in the memory cell array A and the memory cell array B. For example, data of W0 through W7, that is, 2.sup.10 bits, are stored in the memory cell array A, while data of W8 through W15, that is, 2.sup.10 bits, are stored in the memory cell array B.
The bit line selecting circuits 55 are respectively connected to sense amplifier circuits 56 each of which is composed of a plurality of sense amplifiers for detecting information of the respective memory cells, and the sense amplifier circuits 56 are connected to a selector circuit 57 for selecting outputs of the sense amplifier circuits 56 in accordance with a page signal (P0 through P15) based on a page address (A0 through A3). The selector circuit 57 is connected to an output buffer (not shown) so that the output of the selector circuit 57 is sent to an output terminal.
In the memory cell array A, the first through eighth words (W0 through W7) are stored, as described above. Therefore, in each of the word lines (WLiA) of the memory cell array A, the word data W0 through W7 are stored in this order, as illustrated in FIG. 11. Moreover, in each word data, first through 16th page data (P0 through P15) are provided in this order, and in each page data, the first through eighth data (D0 through D7) are provided in this order. Likewise, in the memory cell array B, ninth through 16th word data (W8 through W15) are stored.
The following description will explain a data read operation of the semiconductor memory, while referring to a timing chart in FIG. 12.
At a time t0, an address signal (A0 through A19) to be inputted to input buffers is determined, and a page address (a) is read out. This operation is the same as that in the random access mode.
First, when a row address (A8 through A19) is determined at a time t1, one of pairs of the word lines WLiA and WLiB is made active at a time t2 by the row decoders and the word line driving circuits. Namely, the word lines become "high"-level.
Then, with the determination of the column address (A4 through A7), one (CSj) of column selecting lines CS0 through CS15 becomes active ("high"-level), and a column selecting MOS transistor whose input terminal is connected to the column selecting line CSj becomes in an "ON" state. Subsequently, 128(=8.times.16) memory cells Mmijn (m=0 to 7, n=0 to 15) are selected in accordance with the above address so that pieces of information in the respective memory cells are supplied through the column selecting MOS transistor to the sense amplifier circuit 56. At a time t3, sense amplifier outputs (D0P0 through D7P15) are determined, and the read of the page data of the address designated by a column address and a row address (A4 through A19) finishes. Then, in accordance with a page address (A0 through A3), one of the output signals (P0 through P15) of a page mode decoder becomes active ("high"-level). By doing so, one of the sense amplifier outputs (DmPn) is selected by a selector circuit 57, and is sent to the output terminal (Dm) through the output buffer at a time t4. Thereafter, at a time t5, the page address (A0 through A3) starts changing, data of the sense amplifier outputs are sequentially selected by the selector circuit 57, and are sent to the output terminal through the output buffer at a time t6. Thus, within a time (t6-t4) since the start of the change of the page address (A0 through A3), the mode shifts to the page mode in which data are read at a high speed. Then, when the page address changes from "a" to "a+1", the operation is again carried out in the random access mode, and thereafter, the same step as described above is taken.
Thus, in the case where the column address and the row address A4 through A19 (hereinafter referred to as between-page address) change, data of the output terminal are not determined until outputs of a main data line, the sense amplifier outputs, and the output of the selector are determined, whereas in the case where the page address A0 through A3 (hereinafter referred to as in-page address) change, only a time required for the switching at the selector. Therefore, in the latter case, a page mode which enables high-speed reading is achieved since response to the changes of the in-page address is quick.
The following description will explain details of respective times required for major operations in the semiconductor memory, while referring to FIG. 13. Here, a time since the input of the input address to the semiconductor memory till the determination of the output data is given as 100 percent. A time since the input of the input address through the input buffer till the determination of the input to the decoders (the row decoders, the column decoder, and the page mode decoder) accounts for 10 percent (1 in FIG. 13), an operating time of the decoders accounts for 10 percent (2 in FIG. 13), a time for driving the word lines accounts for 30 percent (3 in FIG. 13), a time for drive of the bit lines and invert of the sense amplifiers due to operations of selected memory cells accounts for 30 percent (4 in FIG. 13), and operating times of the selector and the output buffer account for 20 percent (5 in FIG. 13).
In the case of the random access, all the times of 100 percent are required as described above, whereas in the case of the page access, only the operating times of the input buffer and the page mode decoder with respect to the page address and the operating time of the selector and the output buffer (1+2+5), which account for 40 percent in total, are required for the read operation.
Therefore, as illustrated in FIG. 14, in the read of data from the memory cell array A, 100 percent is required only for the first word. As to the second through eighth words, 40 percent is required for each. Besides, in respect to the memory cell array B, 100 percent is required only for the ninth word which is the top word thereof. On top of this, since the operations of 1 through 4 can be conducted while the data is being read out from the memory cell array A, the ninth word can be outputted immediately after the output of the eighth word.
Thus in the foregoing conventional arrangement, the access to the second and subsequent address in the same page is quickly carried out, but a comparatively long time is required in the access to the top address. Therefore, more speedy access to the top address is now demanded.
Here, the reason why the access time for the top address is long in the high-speed access mode such as the page mode or the serial access mode is that it takes long to drive a word line and bit lines, as illustrated in FIG. 13.
A delay in transition of a word line to or from the "high"-level is substantially in proportion to a product (R.times.C) of a wire resistivity and a wire capacity of the word line, and the wire resistivity and capacity per unit length depend on a manufacturing process. Therefore, to reduce the delay, the word line length should be decreased, or a driving capacity of the word line driving circuit should be increased. Conventionally, to make the access to the top address more speedy, the memory cell array is segmented so that the word line length is decreased, or the driving capacity of the word driving circuit is enhanced.
However, in the case where the memory cell array is segmented so that the word line length decreases, such segmentation causes the word lines to be cut into pieces, thereby requiring more decoders, and as a result, chip areas increase in the semiconductor memory. In the case where the driving capacity of the word line driving circuit is enhanced, there arises a problem of an increase in consumed currency and the like.
The use of the semiconductor memory may not be limited to the use in the high-speed access mode, but it may be used in the random access mode.
Herein, in the case where a ROM (read only memory) is taken as an example of the semiconductor memory, data stored therein are not only one type, but various types of data are stored. The data of various types include those which require a comparatively high read-out speed, and those which may be read out at a lower speed. For example, program data require a relatively high read-out speed, whereas character font data for printout do not require a high read-out speed. In other words, the read-out of program data have to be conducted at a high speed for more speedy processing, whereas the read-out of character font data do not have to be conducted at such a high read-out speed, in relation to a processing speed of a printing device.
However, in conventional cases, such differences in the required read-out speeds depending on the types of the stored data are not particularly taken into consideration, and for example, program data and character font data are stored in the same manner.
The semiconductor memory, as illustrated in FIG. 15, has a memory cell array 61, an address buffer 62, a row decoder 63, a word line driving circuit 64, a column decoder 65, a bit line selecting circuit 66, a sense amplifier circuit 67, and an output buffer 68. In the memory cell array 61, a plurality of memory cells are arrayed in a matrix form. The address buffer 62 holds an address signal supplied from outside and sends it to the row decoder 63 and the column decoder 65. The row decoder 63 decodes content of a predetermined portion of the address signal supplied from the address buffer 62, and outputs a word line selecting signal. The word line driving circuit 64 drives a selected word line in response to the output of the row decoder 63. The column decoder 65 decodes content of another predetermined portion of the address signal supplied from the address buffer 62, and outputs a bit line selecting signal. The bit line selecting circuit 66 connects the sense amplifier circuit 67 with bit lines which are connected with a plurality of predetermined memory cells among a plurality of memory cells connected with a selected word line, in accordance with the output of the column decoder 65. The output buffer 68 outputs the read data to outside, in response to the output of the sense amplifier circuit 67.
As illustrated in FIG. 15, in the conventional ROM, for example, a predetermined region A in the memory cell array is assigned for storing program data and the like, while another predetermined region B is assigned for storing character font data and the like.
However, in the above conventional cases, differences in the required read-out speeds depending on the types of the stored data are not particularly taken into consideration, and for example, program data and character font data are stored in the same manner. Therefore, it is necessary to set the driving capacity of the word line driving circuit in accordance with the read-out speed of data which require the fastest read-out speed. As a result, the capacity is excessive with respect to the other portions for data which require a slower read-out speed, thereby wasting electric power. In other words, though less driving currency is satisfactory, excessive driving currency is used, and hence electric power is wastefully consumed.